1. Field of the Invention
The present invention relates to an operation method for a memory structure, in particular, to an operation method for a non-volatile memory and a method for improving coupling interference of a nitride-based memory.
2. Description of Related Art
A typical non-volatile memory cell has a floating gate and a control gate made by doped polysilicon. The floating gate is disposed between the control gate and a substrate. And, the floating gate is in a floating state and is not electrically connected to any circuit. The floating gate is used to store charges, while the control gate is used to control a data writing/reading operation. The memory cell having the floating gate structure can be used as one bit/cell, single level cell (SLC) or multi-level cell (MLC) and made into a NAND-type array structure.
In addition to the aforementioned floating-gate-based memory cell, a nitride-based memory cell that uses silicon nitride to be a charge trapping layer as a replacement for the polysilicon floating gate has become another mainstream non-volatile memory cell. What makes the nitride-based memory cell more outstanding than the floating-gate-based memory cell is the fabrication process can be easily integrated and the nitride-based memory cell can store 2 bits of data or multi-bits of data. Furthermore, it is often expected that the nitride-based memory cell has no coupling interference issue. The coupling interference issue occurs when the distance between each two devices is too close, thereby resulting in a threshold voltage shift (Vt shift), which is the most important limitation when the aforementioned floating gate based memory cell is continuingly miniaturized.
However, the applicant of this present invention first disclosed that the nitride-based memory structure has similar issue to the aforementioned coupling interference issue. Referring to FIG. 1, FIG. 1 is a diagram illustrating a relationship between currents and voltages measured when performing a reading operation on two different sized memory cells and applying a negative bias voltage to word lines at two sides of the memory cell. In FIG. 1, —▪— represents the measurement results of the currents and the voltages according to a smaller sized memory cell D2; —●— represents the measurement results of the currents and the voltages according to a bigger sized memory cell D1; X axis represents a gate voltage (VG); and Y axis represents a read current. As shown in FIG. 1, after the size of the memory cell is miniaturized, which means a spacing between each two adjacent word lines is shorten, the read current is more prone to be impacted by the bias change of adjacent word lines.
Referring to FIG. 2A and FIG. 2B, FIG. 2A and FIG. 2B are a top view of a bit line layout and a diagram illustrating a relationship between bit counts and Vt shift values for different word lines respectively. FIG. 2A illustrates 8 word lines WL0˜WL7 arranged in parallel, wherein the critical dimension of the word lines is 60 nm. In FIG. 2B, —∘— represents a voltage distribution curve as a whole, and —●—, —▴—, —▾— and —♦— are the voltage distribution curves for the word lines WL1, WL3, WL5 and WL7 respectively. As shown in FIG. 2A and FIG. 2B, when the bits of the word lines WL0, WL2, WL4 and WL6 are programmed to reach a “0” state, the Vt shift values of the adjacent word lines WL1, WL3, WL5 and WL7 increase.
It can be deduced from the experiment results provided by the applicant of the present invention that when miniaturizing the memory cell, if the distance between each two adjacent word lines is too close, it results in the coupling interference issue of the nitride-based memory cell. Moreover, it is known from FIG. 2A and FIG. 2B that the Vt shift values of the word lines, WL1, WL3 and WL5 which have interference from two sides are bigger; while the Vt shift value of the word line WL7 which has interference from one side is smaller.
In addition, referring to FIG. 3A and FIG. 3B, FIG. 3A and FIG. 3B are Vt distribution diagrams for the nitride-based memory cell without consideration of the coupling interference issue and in consideration of the coupling interference issue respectively. As shown in FIG. 3A, numeral 310 represents the Vt distribution curve when the data storage state is “1”; numeral 320 represents the Vt distribution curve when the data storage state is “0”; and an operation window W1 represents the difference between two different data storage states. As shown in FIG. 3B, the coupling interference issue makes the Vt where the data storage state is “1” shift to be a curve marked as numeral 312, and makes the Vt where the data storage state is “0” shift to be another curve marked as numeral 322. At this moment, if comparing an operation window W2 with the operation window W1, W2 is relatively narrower than W1. In light of the above, when defining the operation windows, the coupling interference issue will have different influences to different data storage states of the nitride-based memory.
As discovered by the applicant of the present invention, the coupling interference issue exists in the nitride-based memory, and thereby the Vt of the memory cell is increased and it makes the operation window narrower; therefore, the applicant of the present invention looks for methods to improve the problem, so that the technique development of the non-volatile memory cells can advance forward.